FIG. 1 illustrates one possible approach to providing a ROM circuit. Such a circuit encodes data according to the position of lines connected to the main current terminals of a transistor. Four transistors T are illustrated in FIG. 1 and two lines A and B are provided according to this scheme. Each transistor is able to store one bit of data. In this particular encoding scheme, a “0” is encoded by connecting both of the main current terminals of a transistor to the same line, while a “1” is encoded by connecting the main current terminals of a transistor to different lines. According to this coding scheme, adjacent transistors share a common main current terminal connection, thus reducing the number of connections necessary. This is possible as encoding is based on the connection of one main current terminal of a transistor when compared to the other, rather than on the actual connection of each terminal.
FIG. 2 illustrates an alternative circuit arrangement as described in U.S. Pat. No. 6,636,434, assigned to the assignee herein. Such a circuit allows two bits to be encoded by each transistor in the circuit. Four lines A, B, C and D are provided in this embodiment, and again adjacent transistors share a common main current terminal connection. In this embodiment a coding scheme is used as shown in the following table:
TABLE 1Drain/source connectionsDataof the MOS transistor00ABBACDDC01ADBCCBDA10ACBDCADB11AABBCCDD
Such coding schemes described above require two lines per bit of data that can be encoded. It is generally desirable to reduce the number of lines in such circuits where possible, to reduce the area of the memory, and manufacturing costs.